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Παρασκευή, 17/06/2016   -   Ομιλίες
Σεμινάριο Τμήματος με τίτλο: "Broadening the Research Avenues in Reconfigurable Computing and in Mixed-Criticality Systems", Kyprianos D. Papadimitriou

Στο πλαίσιο της διοργάνωσης των σεμιναρίων του τμήματος, θα πραγματοποιηθεί την Παρασκευή 17/06/2016 και ώρα 12:00 στην αίθουσα Σεμιναρίων του Τμήματος Μηχανικών Η/Υ και Πληροφορικής, ομιλία με τίτλο "Broadening the Research Avenues in Reconfigurable Computing and in Mixed-Criticality Systems". Ομιλητής θα είναι ο κ. Κυπριανός Παπαδημητρίου, Σχολή Ηλεκτρονικών Μηχανικών και Μηχανικών Υπολογιστών (Η.Μ.Μ.Υ.), Πολυτεχνείο Κρήτης.

ΠΕΡΙΛΗΨΗ

Ι will start with an introduction on reconfigurable computing technology and its most representative devices called Field Programmable Gate Arrays (FPGAs). FPGAs are integrated circuits consisting of a large array of uncommitted programmable logic and interconnect, plus large blocks such as memories and Digital Signal Processing (DSP) units that can be configured to implement digital circuits. Their capability to be programmed and reprogrammed in the field to form a digital circuit for executing the application at hand offers an unprecedented advantage over other technologies such as the Application Specific Integrated Circuits (ASICs) that cannot be reprogrammed, and the traditional software microprocessors in which flexibility comes at the expense of limited performance due to fixed instruction set and lack of parallelism. One of their promising feature is the ability to reuse the same hardware for different tasks at different phases of an application execution. Moreover, the tasks can be swapped “on the fly” while part of the hardware continues to operate. This feature is known as run-time or dynamic reconfiguration. Building upon the idea of dynamically reconfiguring a circuit in SRAM-based FPGAs, this talk presents architectural trade-offs of implementing applications in partially reconfigurable (PR) FPGA-based systems and proposes new avenues for its use. Initially, a novel way to schedule tasks in PR FPGAs is presented, which was evaluated within the context of a simulation framework. In addition, a real-world experimental framework was built, which was used as the basis to formulate a theoretical model for the early assessment of the reconfiguration overhead. I will then describe a novel way to exploit the PR technology in a specific application domain. All aspects of the present research have been verified with experiments from different setups using partially reconfigurable FPGA platforms. I will continue with my latest research, which includes the development of a runtime manager for servicing systems combining software and reconfigurable hardware, and the use of on-chip networks in mixed-criticality systems.

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